1. Field of the Invention
This invention relates generally to the reduction of power usage by processing units. More particularly, it relates to the reduction of power usage by a processing unit while allowing the clock cycles of the processing unit to occur at full rate.
2. Background of Related Art
The increasing use of portable devices has generated a need in the industry for low power processing units. The lower power the processing unit, the longer the useful life of the portable device and/or the smaller the required battery.
Moreover, continued integration of devices has generated an environment wherein multiple processing units or other devices perform separate tasks but in coordination with one another. Oftentimes, the processing units and/or other devices communicate based on common timing or within certain time frames. Conventionally, a continuously operating master clock is typically required to maintain communications between the separate devices or circuits.
One common technique for reducing unnecessary power dissipation is to qualify the master clock input to devices which are not required for the particular application(s). According to this technique, the master clock is withheld from the unused devices. Another similar conventional technique halts the instruction cycles of an unused processing device entirely. However, these techniques either prevent communication with the unused processing devices, or require the processing device to power up to receive the communications.
Another conventional approach to reduce power consumption allows the master clock to operate at full rate for certain processing units or other devices, but stretches the master clock signal for input to unused or powered-down devices. This technique effectively reduces the frequency of the instruction clock for those processing units or other devices which are not needed or are otherwise in a power down mode. However, reduction of the frequency of the instruction clock in a processing unit typically requires cumbersome circuitry to stretch the master clock signal, and slows communications between powered-down devices and fully operating devices, detrimentally affecting the application program(s) running on the full-rate devices.
There is a need for a method and apparatus to allow the reduction of power in a processing unit without the need for clock stretching circuitry and/or without affecting the performance of other devices.